Title :
New Mechanism of LER Formation in Gate Process
Author :
Yabata, Atsushi ; Koike, Osamu ; Hashimoto, Jun ; Kurachi, Ikuo
Author_Institution :
Miyagi Oki Electr. Co., Ltd., Miyagi
Abstract :
Influence of each process for gate LER has been studied and evaluated by 3D AFM. From the result, PR LER was found to be larger than any other process and major cause of LER formation. As another possible parameter, effect of poly-Si material has been also evaluated. It provided that LER was closely related to number of grain boundaries of poly-Si. The mechanism of LER formation by grain boundary is following. When sputtering yield at the site of grain boundary is assumed to be very high, grain boundaries must be easy to be transferred to the gate pattern during etching and consequently high LER. Therefore, It is very important for improving LER to reduce grain boundary. On the other hand, poly-Si etching with high bias power is able to reduce gate LER. That indicates grain boundary is controlled by high incident ion sputtering.
Keywords :
MOSFET; atomic force microscopy; grain boundaries; sputter etching; 3D AFM; etching; gate process; grain boundaries; high incident ion sputtering; line edge roughness; Atomic force microscopy; Crystallization; Grain boundaries; MOSFETs; Plasma applications; Plasma measurements; Response surface methodology; Sputter etching; Sputtering; Transistors;
Conference_Titel :
Semiconductor Manufacturing, 2006. ISSM 2006. IEEE International Symposium on
Conference_Location :
Tokyo
Print_ISBN :
978-4-9904138-0-4
DOI :
10.1109/ISSM.2006.4493033
