• DocumentCode
    3293604
  • Title

    Elimination of Vmin failures in 0.15um logic process

  • Author

    Yee Ming Chan ; Pik Yee Ng ; Ling Yun Miao ; Hyun Gu Yoon ; Kin San Pey

  • Author_Institution
    Syst. on Silicon Manuf. Co. Pte Ltd., Singapore
  • fYear
    2006
  • fDate
    25-27 Sept. 2006
  • Firstpage
    152
  • Lastpage
    155
  • Abstract
    A significant increase in Vmin failures was observed with device shrinkage. These Vmin failures were observed to be random on wafer and were highly correlated to IDDQ and Delta IDDQ failures. A strong correlation of Vmin failures to STI depth was found. Fault isolation showed that the root cause of our Vmin failures was due to stress related dislocations. Structural and electrical characterizations were used to confirm the proposed root cause mechanism. This paper presents a simple and cost effective method in resolving high Vmin failure rate in production devices. With the new process, a significant yield gain was achieved.
  • Keywords
    ULSI; fault diagnosis; isolation technology; ULSI; device shrinkage; fault isolation; isolation trench depth; Costs; Logic devices; Manufacturing processes; Oxidation; Plasma temperature; Production; Silicon; Stress; Testing; Voltage;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Semiconductor Manufacturing, 2006. ISSM 2006. IEEE International Symposium on
  • Conference_Location
    Tokyo
  • ISSN
    1523-553X
  • Print_ISBN
    978-4-9904138-0-4
  • Type

    conf

  • DOI
    10.1109/ISSM.2006.4493047
  • Filename
    4493047
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3293604