• DocumentCode
    3293640
  • Title

    Method of extracting high-resolution digital Moiré fringe in warpage measurement

  • Author

    Ping Zhong ; Song Chenjie ; Luo Nian

  • Author_Institution
    Dept. of Appl. Phys., Dong Hua Univ., Shanghai, China
  • fYear
    2009
  • fDate
    6-10 July 2009
  • Firstpage
    527
  • Lastpage
    530
  • Abstract
    Thermally induced stresses play a very important role in controlling the structural reliability of microchip packages. To address this issue, the shadow moireacute interferometry is developed, which has been widely used in the field of observation for its real-time and high resolution. But how to extract the moireacute fringes by using digital image processing method from a original Moireacute fringe pattern is the key to accurate measurement of the warpage. The paper mainly concentrates on the method of effectively extracting the shadow moire fringes from interference pattern produced by warpage of the PWB board and BGA package. Firstly, the low passing filtering and the dynamic threshold binarization proposed in this paper are applied to preprocess the moire pattern. Then, the medial axis transformation and pruning algorithm applied to extract skeleton of moireacute fringe have been put forward. Because the forficate fringes and noise fringes are main factors to affect precision of measurement, a effective main fringe extracting algorithm is proposed, which not only identifies and removes the forficate fringes and noise fringes from the main fringes, but also can connect the crack fringes which are hardly avoided after thinning operation. Finally, the information of warpage can be obtained from the location and orientation of moireacute fringes. The three-dimensional delineation of detected object is resolved according to the moireacute fringes extracted from shadow moireacute pattern.
  • Keywords
    ball grid arrays; circuit analysis computing; circuit reliability; light interference; low-pass filters; moire fringes; object detection; printed circuits; thermal stresses; BGA package; PWB board; ball grid arrays; digital image processing method; dynamic threshold binarization method; high-resolution digital moire fringe extraction; interference pattern; low passing filtering; medial axis transformation; microchip packages; object detection; pruning algorithm; shadow moireacute interferometry; structural reliability; thermal induced stresses; three-dimensional delineation; warpage measurement; Data mining; Digital images; Filtering; Interference; Interferometry; Low pass filters; Packaging; Skeleton; Stress control; Thermal stresses;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Physical and Failure Analysis of Integrated Circuits, 2009. IPFA 2009. 16th IEEE International Symposium on the
  • Conference_Location
    Suzhou, Jiangsu
  • ISSN
    1946-1542
  • Print_ISBN
    978-1-4244-3911-9
  • Electronic_ISBN
    1946-1542
  • Type

    conf

  • DOI
    10.1109/IPFA.2009.5232591
  • Filename
    5232591