Title :
Improvement method of the machine-model ESD robustness for a smart power IC
Author :
Song, Jong-Kyu ; Kim, Dae-Woo ; Kim, Jong-Min ; Won-Young Jung ; Wee, Jae-Kyung
Author_Institution :
Tech. Eng. Divsion, Dongbu HiTek Semicond., South Korea
Abstract :
The failure behavior of the smart power IC using a 0.35 mum bipolar-CMOS-DMOS was investigated, and the major ESD failure spots were found at the corner of the guard-ring structure and the high-voltage transistor, which is connected between the different power domains (Vdd-Vcc). The mechanism of these failures is investigated by the T-CAD simulation, and the method to improve the Machine Model (MM) Robustness is provided. To improve the MM level, the power rail was modified for blocking an unexpected ESD current path using the cost-effective metal revision. This increased MM ESD robustness significantly from 150V to 230V.
Keywords :
CMOS integrated circuits; bipolar integrated circuits; electrostatic discharge; power integrated circuits; T-CAD simulation; bipolar-CMOS-DMOS; cost-effective metal revision; electrostatic discharge; machine-model ESD robustness; size 0.35 mum; voltage 150 V to 230 V; Electrostatic discharge; Failure analysis; Integrated circuit modeling; Power engineering and energy; Power integrated circuits; Protection; RLC circuits; Robustness; Stress; Testing;
Conference_Titel :
Physical and Failure Analysis of Integrated Circuits, 2009. IPFA 2009. 16th IEEE International Symposium on the
Conference_Location :
Suzhou, Jiangsu
Print_ISBN :
978-1-4244-3911-9
Electronic_ISBN :
1946-1542
DOI :
10.1109/IPFA.2009.5232598
