Title :
A realistic architecture for timed testing
Author :
Petitjean, Eric ; Fouchal, Hacène
Author_Institution :
RESYCOM-LERI, Univ. de Reims Champagne-Ardenne, France
Abstract :
The aim of this paper is to present a convenient test architecture for the purpose of testing timed systems. A timed system is described as a timed automaton which is expressed as a region graph. This latter is then translated into a flattened automaton. Test sequences are derived from the flattened automaton. In order to check the conformity of a real life implementation, we detail the test architecture needed to execute the derived test sequences. This architecture considers the behaviour part as well as the timed part of the system
Keywords :
automata theory; formal specification; formal verification; program testing; real-time systems; sequences; behaviour part; flattened automaton; realistic architecture; region graph; test architecture; test sequences; timed automaton; timed system testing; Architecture; Automata; Automatic testing; Life testing; Logic testing; Read only memory; Real time systems; Software testing; System testing; Tellurium;
Conference_Titel :
Engineering of Complex Computer Systems, 1999. ICECCS '99. Fifth IEEE International Conference on
Conference_Location :
Las Vegas, NV
Print_ISBN :
0-7695-0434-5
DOI :
10.1109/ICECCS.1999.802855
