Title :
A simple and fast parallel round-robin arbiter for high-speed switch control and scheduling
Author :
Zheng, S.Q. ; Yang, Mei ; Blanton, John ; Golla, Prasad ; Verchere, Dominique
Author_Institution :
Dept. of Comput. Sci., Texas Univ. at Dallas, Richardson, TX, USA
Abstract :
The design of a fast and fair arbiter is critical to the efficiency of the scheduling algorithm, which is the key to the performance of a high-speed packet switch. In this paper, we propose a parallel round-robin arbiter (PRRA) design, based on a binary-tree structure. We show that our design is simpler and faster than existing round-robin arbiter designs.
Keywords :
asynchronous circuits; electronic switching systems; logic design; packet switching; scheduling; trees (mathematics); PRRA; binary-tree structure; fast packet switch; fast/fair arbiter; high-speed packet switch; high-speed scheduling; high-speed switch control; parallel round-robin arbiter; Algorithm design and analysis; Delay; Hardware; High performance computing; Packet switching; Processor scheduling; Scheduling algorithm; Signal design; Switches; Technological innovation;
Conference_Titel :
Circuits and Systems, 2002. MWSCAS-2002. The 2002 45th Midwest Symposium on
Print_ISBN :
0-7803-7523-8
DOI :
10.1109/MWSCAS.2002.1186951
