Determination of yield bounds prior to routing

Integrated circuit manufacturing complexities have resulted in decreasing product yields and reliabilities. This process has been accelerated with the advent of very deep sub-micron technologies coupled with the introduction of newer materials and technologies like copper interconnects, silicon-on-insulator and increased wafer sizes. The need to improve product yields has been recognized and currently some yield enhancement techniques are used in industry CAD tools. Still, the significant increase in problem size implies that considerable time and effort can be saved if the designer could predict the yield of each design stage. In this paper we undertake an effort to derive bounds on the yield of the routing for a given placement. When the design is routed, resulting in a yield which is significantly smaller than the bound, the designer can choose to change the router cost functions, modify the placement or even re-design the unit in an attempt to increase the yield. We compare the bounds on yield obtained for a set of standard benchmarks against exact yield values for the “vanilla” routings, and the run times needed to calculate the two. The results indicate that reasonably good estimates of yield can be obtained in significantly lower amounts of run time. The accuracy of the estimates increases when larger designs are considered as the simplifying assumptions made and the model no longer influences the estimates significantly