Title :
Power consumption behaviour of multiplier block algorithms
Author :
Demirsoy, Suleyman Sirrr ; Dempster, Andrew G. ; Kale, Izzet
Author_Institution :
Dept. of Electron. Syst., Westminster Univ., London, UK
Abstract :
Multiplier blocks have been used primarily for the reduction of circuit complexity. Using new algorithms, it has been shown that they can also be used for effective reduction of power consumption in digital filter circuits. In this paper, the new GP score method is used as a relative power measure to compare digital filter multiplier blocks designed using the BHM, RAGn and Cl algorithms.
Keywords :
digital arithmetic; digital filters; low-power electronics; multiplying circuits; BHM algorithm; C1 algorithm; GP score method; RAGn algorithm; digital filter circuits; digital filter multiplier blocks; multiplier block algorithms; power consumption behaviour; Adders; Algorithm design and analysis; Circuits; Clocks; Digital filters; Digital signal processing; Energy consumption; MATLAB; Power measurement; Very large scale integration;
Conference_Titel :
Circuits and Systems, 2002. MWSCAS-2002. The 2002 45th Midwest Symposium on
Print_ISBN :
0-7803-7523-8
DOI :
10.1109/MWSCAS.2002.1186955
