Title :
A Hierarchical Bridging Fault Extraction Approach For VLSI Circuit Layouts
Author :
Chen, Tzuhao ; Hajj, Ibrahim N.
Keywords :
Bridge circuits; Circuit faults; Circuit testing; Data mining; Logic circuits; Logic design; Logic gates; Logic testing; Routing; Very large scale integration;
Conference_Titel :
VLSI Technology, Systems, and Applications, 1997. Proceedings of Technical Papers. 1997 International Symposium on
Conference_Location :
Taipei, Taiwan
Print_ISBN :
0-7803-4131-7
DOI :
10.1109/VTSA.1997.614932
