Yield estimation of VLSI circuits with downscaled layouts

Author

Pleskacz, Witold A.

Author_Institution

Inst. of Microelectron. & Optoelectron., Warsaw Univ. of Technol., Poland

fYear

1999

fDate

36465

Firstpage

55

Lastpage

60

Abstract

This paper describes the yield estimation approach to layout scaling of submicron VLSI circuits. The presented method makes it feasible to find a scaling factor of the IC design which is optimal from the manufacturing yield point of view. It also allows us to reduce time-consuming extraction of the critical area functions. Examples of yield calculations using the proposed method are presented as well

Keywords

CMOS integrated circuits; VLSI; circuit optimisation; fault diagnosis; integrated circuit layout; integrated circuit metallisation; integrated circuit modelling; integrated circuit yield; 0.8 mum; CMOS technology designs; IC design; Poisson based yield model; critical area function extraction; layout scaling; manufacturing yield; metal layers; optimal downscaling; scaling factor; submicron VLSI circuits; yield estimation; Circuit faults; Conducting materials; Cost function; Integrated circuit layout; Integrated circuit testing; Manufacturing processes; Microelectronics; Shape; Very large scale integration; Yield estimation;

fLanguage

English

Publisher

ieee

Conference_Titel

Defect and Fault Tolerance in VLSI Systems, 1999. DFT '99. International Symposium on

Conference_Location

Albuquerque, NM

ISSN

1550-5774

Print_ISBN

0-7695-0325-x

Type

conf

DOI

10.1109/DFTVS.1999.802869

Filename

802869