Design of a novel dual pathway ESD protection device using ISE-TCAD

Author

Zhang Bing ; Chai Changchun ; Ding Ruixue ; Xi Xiaowen

Author_Institution

Key Lab. of Minist. of Educ. for Wide Band-gap, Semicond. Mater. & Devices, Xidian Univ., Xi´an, China

fYear

2009

fDate

6-10 July 2009

Firstpage

426

Lastpage

429

Abstract

A novel dual pathway electrostatic discharge (ESD) protection device based on 0.6 mum CMOS p-well technology has been designed and fabricated according to the ISE-TCAD simulation tool and the C-R method. The new device was verified by a multi-project wafer (MPW) fabrication and tested by the transmission line pulse (TLP) generator system. The results show that new device has lower trigger voltage, smaller chip area and a higher ESD failure voltage compared with those of gate grounded NMOS (ggNMOS) protection circuits with the same MPW. The voltage up to 5 KV under human-body mode (HBM) test has been obtained.

Keywords

CMOS integrated circuits; electronic engineering computing; electrostatic discharge; technology CAD (electronics); C-R method; CMOS technology; ISE-TCAD simulation tool; dual pathway ESD protection device; electrostatic discharge; gate grounded NMOS protection circuits; human-body mode test; multiproject wafer fabrication; size 0.6 mum; transmission line pulse generator system; CMOS technology; Circuit testing; Distributed parameter circuits; Electrostatic discharge; Fabrication; MOS devices; Protection; Pulse generation; System testing; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Physical and Failure Analysis of Integrated Circuits, 2009. IPFA 2009. 16th IEEE International Symposium on the

Conference_Location

Suzhou, Jiangsu

ISSN

1946-1542

Print_ISBN

978-1-4244-3911-9

Electronic_ISBN

1946-1542

Type

conf

DOI

10.1109/IPFA.2009.5232615

Filename

5232615