Title :
A zero aliasing built-in self test technique for delay fault testing
Author :
Tsiatouhas, Y. ; Haniotakis, Th
Author_Institution :
ISD S.A., Athens, Greece
Abstract :
A zero aliasing built-in self-test (BIST) approach to detect timing related failures in VLSI circuits is proposed. The BIST scheme is based on a transition detector and is able to detect timing related failures resulting in shorter than expected as well as larger than expected delay faults
Keywords :
VLSI; automatic test pattern generation; built-in self test; failure analysis; fault diagnosis; integrated circuit testing; logic testing; timing; VLSI circuits; delay fault testing; digital circuits; test pattern generator; timing related failures; transition detector; zero aliasing BIST approach; Automatic testing; Built-in self-test; Circuit faults; Circuit testing; Delay; Detectors; Electrical fault detection; Fault detection; Timing; Very large scale integration;
Conference_Titel :
Defect and Fault Tolerance in VLSI Systems, 1999. DFT '99. International Symposium on
Conference_Location :
Albuquerque, NM
Print_ISBN :
0-7695-0325-x
DOI :
10.1109/DFTVS.1999.802874
