Title :
The enhancement of power-rail ESD clamp circuit with gate-substrate-triggered technique
Author :
Yeh, Chih-Ting ; Liang, Yung-Chih ; Jiang, Zhe-Wei ; Chang, Xin-Yuan
Author_Institution :
Circuit Design Dept., Ind. Technol. Res. Inst. (STC ITRI), Hsinchu, Taiwan
Abstract :
In this work, the power-rail ESD clamp circuit fabricated in 130 nm CMOS process is investigated. In order to improve the ESD protection ability, the power-rail ESD clamp circuit with gate-substrate-triggered is proposed. By comparing with the other two techniques, gate-driven and substrate-triggered, it is shown that the secondary breakdown current of the power-rail ESD clamp circuit with gate-substrate-triggered is improved by 20%.
Keywords :
CMOS integrated circuits; electrostatic discharge; integrated circuit reliability; protection; CMOS IC reliability; CMOS process; ESD protection ability; electrostatic discharge protection; gate-substrate-triggered technique; power-rail ESD clamp circuit; secondary breakdown current; CMOS technology; Circuit testing; Clamps; Electrostatic discharge; MOS devices; Protection; Robustness; Stress; Substrates; Voltage;
Conference_Titel :
Physical and Failure Analysis of Integrated Circuits, 2009. IPFA 2009. 16th IEEE International Symposium on the
Conference_Location :
Suzhou, Jiangsu
Print_ISBN :
978-1-4244-3911-9
Electronic_ISBN :
1946-1542
DOI :
10.1109/IPFA.2009.5232629
