Title :
RAMSES: a fast memory fault simulator
Author :
Wu, Chi-Feng ; Huang, Chih-Tsun ; Wu, Cheng-Wen
Author_Institution :
Dept. of Electr. Eng., Nat. Tsing Hua Univ., Hsinchu, Taiwan
Abstract :
In this paper, we present a memory fault simulator called the Random Access Memory Simulator for Error Screening (RAMSES). Although it was designed based on some well-known memory fault models, the algorithm that we developed ensures that new fault models can be included easily by adding new fault descriptors instead of modifying the algorithm or program. With RAMSES, the time complexity of memory fault simulation is improved from O(N3) to O(N2), where N is the memory capacity in terns of bits. Our approach requires only a small amount of extra memory space. Simulation results by RAMSES show that running the proposed cocktail-March tests can significantly reduce the test time. With the help of RAMSES, an efficient test algorithm called March-CW was developed for word-oriented memories
Keywords :
automatic testing; circuit simulation; computational complexity; fault simulation; integrated circuit testing; integrated memory circuits; random-access storage; March-CW test algorithm; RAMSES; cocktail-March tests; error screening; fast memory fault simulator; fault descriptors; memory fault models; random access memory simulator; time complexity; word-oriented memories; Algorithm design and analysis; Analytical models; Automatic testing; Built-in self-test; Costs; Design for testability; Engines; Logic testing; Random access memory; Semiconductor device testing;
Conference_Titel :
Defect and Fault Tolerance in VLSI Systems, 1999. DFT '99. International Symposium on
Conference_Location :
Albuquerque, NM
Print_ISBN :
0-7695-0325-x
DOI :
10.1109/DFTVS.1999.802882