Title :
A new memory-reduced architecture design for log-MAP algorithm in turbo decoding
Author :
Tsai, Tsung-Han ; Lin, Cheng-Hung
Author_Institution :
Dept. of Electr. Eng., Nat. Central Univ., Chung-li, Taiwan
fDate :
31 May-2 June 2004
Abstract :
In coding theory, turbo codes have been the breakthrough in recent years. Among these, the MAP (maximum a posteriori) algorithm is a powerful SISO (soft-input soft-output) algorithm for turbo decoding. However, MAP decoders of the turbo decoding consume large memories in hardware implementation. This work presents a new architecture for memory reduction in log-MAP (logarithm-MAP) algorithm. Based on the scheduling analysis, the backward recursion can be reversed in order to be directly operated on with forward recursion. The comparison result shows it can effectively reduce the memory size up to half size of the previous works. In addition, we also simplify the memory data access without extra address generators.
Keywords :
iterative decoding; maximum likelihood decoding; memory architecture; recursive estimation; turbo codes; MAP; backward recursion; coding theory; forward recursion; hardware implementation; large memory consumption; log-MAP algorithm; maximum a posteriori algorithm; memory data access; memory reduction; memory size; memory-reduced architecture design; scheduling analysis; soft-input soft-output algorithm; turbo decoding; Algorithm design and analysis; Bit error rate; Hardware; Iterative algorithms; Iterative decoding; Memory architecture; Performance gain; Scheduling; Turbo codes; Viterbi algorithm;
Conference_Titel :
Emerging Technologies: Frontiers of Mobile and Wireless Communication, 2004. Proceedings of the IEEE 6th Circuits and Systems Symposium on
Print_ISBN :
0-7803-7938-1
DOI :
10.1109/CASSET.2004.1321961
