Failure analysis of EOS damage case study

Nowadays, with the development of silicon fabrication technology from 130 um technology in early 70´s till present 45 nm technology, the geometries of transistors shrink smaller and smaller, IC devices become more sensitive to electrostatic discharge, or electrical overstress, i.e. ESD/EOS. ESD/EOS, therefore, is one of the major causes of device failures in the semiconductor industry. Tremendous efforts are being made by both component/system level design and IC supplier / EMS/ OEM manufactory control. Failure analysis plays its unique role to validate ESD/EOS failure mechanism and drive the mitigation of ESD/EOS failures. In this paper, real case was stated to show the contribution of our FA results for ATE test program & IC circuit design debugging.