Title :
A SCR-buried BJT device for robust ESD protection with high latchup immunity in high-voltage technology
Author :
Huang, Chih-Yao ; Chen, Quo-Ker ; Lai, Ming-Fang ; Chiu, Fu-Chien ; Tseng, Jen-Chou
Author_Institution :
Dept. of Electron. Eng., Ching Yuan Univ., Taoyuan, Taiwan
Abstract :
An SCR-buried BJT with a high holding voltage is developed for ESD protection in a 0.6 mum high voltage 10 V process. This device simply consists of a floating P+ diffusion buried in a parasitic NPN BJT. A robust 6~7KV ESD threshold and high-latchup-immune 15~18V holding voltage can be achieved by layout optimization of the anode-to-floating- P+-diffusion spacing and this P+ diffusion width.
Keywords :
bipolar transistors; electrostatic discharge; high-voltage engineering; P+ diffusion width; SCR-buried BJT device; anode-to-floating-P+-diffusion spacing; high latchup immunity; high-voltage technology; robust ESD protection; Anodes; CMOS technology; Electronics industry; Electrostatic discharge; MOS devices; Manufacturing industries; Protection; Robustness; Threshold voltage; Thyristors;
Conference_Titel :
Physical and Failure Analysis of Integrated Circuits, 2009. IPFA 2009. 16th IEEE International Symposium on the
Conference_Location :
Suzhou, Jiangsu
Print_ISBN :
978-1-4244-3911-9
Electronic_ISBN :
1946-1542
DOI :
10.1109/IPFA.2009.5232632
