A CMOS-based logic cell for the implementation of self-checking FPGAs

Author

Lala, P.K. ; Singh, A. ; Walker, A.

Author_Institution

Dept. of Electr. Eng., Univ. of South Florida, Tampa, FL, USA

fYear

1999

fDate

36465

Firstpage

238

Lastpage

246

Abstract

This paper proposes a logic cell that can be used as a building block for online testable FPGAs. The proposed logic cell consists of two 2-to-1 multiplexers, three 4-to-1 multiplexers and a D flip-flop. The cell has been designed using Differential Cascode Voltage Switch (DCVS) logic. It is self-checking for all single transistor stuck-on and stuck-off faults as well as stuck-at faults at the inputs of each multiplexer and the D flip-flop. The multiplexers and the D flip-flop provide either correct (complementary) output in the absence of above-mentioned faults or identical outputs in the presence of fault

Keywords

CMOS logic circuits; automatic testing; field programmable gate arrays; flip-flops; integrated circuit testing; logic testing; CMOS-based logic cell; D flip-flop; DCVS logic; differential cascode voltage switch logic; multiplexers; online testable FPGA; self-checking FPGAs; stuck-at faults; transistor stuck-on faults; transistor stuckoff faults; Circuit faults; Circuit testing; Electrical fault detection; Fault detection; Field programmable gate arrays; Flip-flops; Logic testing; Multiplexing; Switches; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Defect and Fault Tolerance in VLSI Systems, 1999. DFT '99. International Symposium on

Conference_Location

Albuquerque, NM

ISSN

1550-5774

Print_ISBN

0-7695-0325-x

Type

conf

DOI

10.1109/DFTVS.1999.802890

Filename

802890