DocumentCode :
3294580
Title :
Power consumption in fast dividers using time shared TMR
Author :
Gallagher, W. Lynn ; Swartzlander, Earl E., Jr.
Author_Institution :
Dept. of Electr. & Comput. Eng., Texas Univ., Austin, TX, USA
fYear :
1999
fDate :
36465
Firstpage :
256
Lastpage :
264
Abstract :
The Newton-Raphson algorithm and Goldschmidt´s algorithm (series expansion) are two popular methods of implementing division. Both are based on multiplication and converge quadratically to the result over several iterations. Applying time shared triple modular redundancy (TSTMR), a fault tolerance technique, to such a divider requires using a smaller multiplier and triplicating the divider circuit. To reduce division latency, the division algorithm can be modified to use lower precision multiplications during early iterations. This work summarizes and compares several important properties of these dividers: latency, area, average power dissipation and energy per divide
Keywords :
Newton-Raphson method; dividing circuits; fault tolerance; low-power electronics; redundancy; Goldschmidt´s algorithm; Newton-Raphson algorithm; area; average power dissipation; dividers; division latency; fault tolerance technique; power consumption; precision; time shared TMR; time shared triple modular redundancy; Arithmetic; Circuits; Convergence; Delay; Energy consumption; Fault tolerance; Fault tolerant systems; Iterative algorithms; Read only memory; Redundancy;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Defect and Fault Tolerance in VLSI Systems, 1999. DFT '99. International Symposium on
Conference_Location :
Albuquerque, NM
ISSN :
1550-5774
Print_ISBN :
0-7695-0325-x
Type :
conf
DOI :
10.1109/DFTVS.1999.802892
Filename :
802892
Link To Document :
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