Fault-tolerant refresh power reduction of DRAMs for quasi-nonvolatile data retention

A quasi-nonvolatile memory system based on commercially available low-power dynamic random access memory (DRAM) technology is proposed and demonstrated. By applying a powerful one-shot Reed-Solomon error correction code (ECC) to the data stored in the DRAM, the refresh rate and memory system power usage can be greatly reduced while still maintaining data integrity. An adaptive refresh rate controller was developed in order to ensure robustness against the variations in data retention time due to perturbation effects such as DRAM part-to-part variations, environmental changes and data pattern sensitivity, while at the same time minimizing power usage. By checking for data failures among a small subset of data bits which are dynamically selected at the beginning of each use of the system, the state of the perturbation effects are predicted and used to adjust the refresh rate. As a result, a system was developed that provides reliability equivalent to standard DRAM systems while greatly (10-100X) reducing the refresh power. Experimental results of a test system are presented