Novel CMOS ternary flip-flops using double pass-transistor logic

Novel CMOS D-type and modular algebra-based edge-triggered ternary flip-flops using double pass-transistor logic(DPL), are presented. In the proposed circuit scheme, literal functions are also realized by using traditional MOS transistors without any modification of the thresholds. The DPL-based flip-flop has some favourable properties: perfectly symmetrical structure, full logic swing and the maximum possible noise margins, the less complex structure, and no static power consumption. The proposed D-type flip-flop consists of complementary inputs/outputs and is thus a dual rail ternary flip-flop. The modular algebra-based flip-flop can give triple-rail ternary complementary outputs. HSPICE simulations using 0.35μm CMOS technology and a 3V power supply demonstrate the effectiveness of the proposed design approach.