Reliability concern induced by TOW and TIM overlay issue in EEPROM

Author

Fan, Weihai ; Chiang, Shunwang ; Xie, Stephen ; Hu, Shaha

Author_Institution

Semicond. Manuf. Int. Corp., Shanghai, China

fYear

2009

fDate

6-10 July 2009

Firstpage

294

Lastpage

297

Abstract

We investigated the overlay effect of TOW (tunnel oxide window) and TIM (tunneling implant) on the reliability of EEPROM product. Normally soft failure could be observed on the zero time state devices. The two key reliability indices for non-volatile memory are cycling and data retention. These reliability performances are impacted by the TIM/TOW overlay even with the more strict pre-screening method had been applied due to early failure screening. In this paper a failure model was proposed to explain the failure mechanism. The marginal reliability performance and the faster device degradation during write/erase cycling or baking could result from the overlay issue of TOW and TIM.

Keywords

EPROM; integrated circuit reliability; random-access storage; tunnelling; EEPROM reliability; TIM overlay effect; TOW overlay effect; failure mechanism; nonvolatile memory; tunnel oxide window; tunneling implant; write-erase cycling; zero time state device; EPROM; Etching; Failure analysis; Implants; Nonvolatile memory; Semiconductor device manufacture; Semiconductor device reliability; Testing; Tunneling; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Physical and Failure Analysis of Integrated Circuits, 2009. IPFA 2009. 16th IEEE International Symposium on the

Conference_Location

Suzhou, Jiangsu

ISSN

1946-1542

Print_ISBN

978-1-4244-3911-9

Electronic_ISBN

1946-1542

Type

conf

DOI

10.1109/IPFA.2009.5232647

Filename

5232647