DocumentCode :
3294777
Title :
Good processor identification in two-dimensional grids
Author :
Meyer, Fred J. ; Lombardi, Fabrizio ; Zhao, Jun
Author_Institution :
Dept. of Electr. & Comput. Eng., Northeastern Univ., Boston, MA, USA
fYear :
1999
fDate :
36465
Firstpage :
348
Lastpage :
356
Abstract :
We examine the problem of identifying good processors in self-testing two-dimensional grid systems. The grids have boundaries (not wrap-around) and degree 8. Our diagnostic objective is to identify at least one fault-free processor. From this, at feast one faulty processor could be identified and it would be possible to sequentially diagnose the system by repeated repair. We establish an upper bound on the worst case maximum number of faults while still being able to meet the diagnostic goal with an ideal diagnosis algorithm. A straightforward ideal diagnosis algorithm would have exponential complexity and would involve 16 parallel rounds of processor testing. We give a test schedule with at most 6 parallel rounds of testing. This test schedule tolerates asymptotically as many faults as an ideal algorithm (by a constant factor). The new test schedule will also work for grids with degree 4, which have inferior diagnostic potential
Keywords :
VLSI; automatic testing; fault diagnosis; integrated circuit testing; logic testing; microprocessor chips; multiprocessing systems; diagnosis algorithm; fault-free processor identification; processor testing; self-testing 2D grid systems; test schedule; two-dimensional grids; Built-in self-test; Fault diagnosis; Field programmable gate arrays; Grid computing; Processor scheduling; Scheduling algorithm; Sequential diagnosis; Software; System testing; Upper bound;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Defect and Fault Tolerance in VLSI Systems, 1999. DFT '99. International Symposium on
Conference_Location :
Albuquerque, NM
ISSN :
1550-5774
Print_ISBN :
0-7695-0325-x
Type :
conf
DOI :
10.1109/DFTVS.1999.802902
Filename :
802902
Link To Document :
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