DocumentCode
3295001
Title
Systolic equalizer structures
Author
Sexton, Thomas A. ; Parviainen, Jan A.
Volume
3
fYear
2002
fDate
4-7 Aug. 2002
Abstract
Algorithms for the detection of an 8-PSK signal distorted by passage through a cellular radio channel are reviewed. The goal is to provide performance and VLSI implementation comparisons. The main contribution of this paper is the presentation of a systolic equalizer for Viterbi equalization of an 8-PSK signal. Variations of the systolic linear array are also discussed.
Keywords
VLSI; Viterbi detection; application specific integrated circuits; cellular radio; digital signal processing chips; equalisers; phase shift keying; systolic arrays; 8-PSK signal detection; ASIC; DSP chip; VLSI implementation comparisons; Viterbi equalization; cellular radio channel; performance comparisons; systolic equalizer structures; systolic linear array; Baseband; Decoding; Detectors; Distortion; Equalizers; Feedback; GSM; Land mobile radio cellular systems; Mobile handsets; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 2002. MWSCAS-2002. The 2002 45th Midwest Symposium on
Print_ISBN
0-7803-7523-8
Type
conf
DOI
10.1109/MWSCAS.2002.1187001
Filename
1187001
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