• DocumentCode
    3295010
  • Title

    Partial Sum Based Algorithm for the Discrete Cosine Transform

  • Author

    Tian, Mao ; Li, Guang-Jun ; Peng, Qi-Zong

  • Author_Institution
    Univ. of Electron. Sci. & Technol. of China, Chengdu
  • fYear
    2006
  • fDate
    38869
  • Firstpage
    1094
  • Lastpage
    1097
  • Abstract
    In this paper, a fast algorithm and its corresponding hardware structure are developed for the 2Mtimes2M type discrete cosine transform. The transform output is transformed into a mul-add format by the definition of the 2-D DCT/IDCT. The output data set is partitioned into several subsets each having the same multiplicands that we call partial sum. By computing partial sum, the addition and multiplication operation times can be greatly reduced. In final, its corresponding hardware architecture is presented for VLSI implementation. The synthesis result shows that the algorithm is efficient and reliable
  • Keywords
    VLSI; adders; discrete cosine transforms; multiplying circuits; VLSI implementation; addition operation; discrete cosine transform; hardware architecture; mul-add format; multiplication operation; partial sum based algorithm; Computer architecture; Costs; Discrete cosine transforms; Discrete transforms; Field programmable gate arrays; Hardware; Partitioning algorithms; Throughput; Very large scale integration;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    ITS Telecommunications Proceedings, 2006 6th International Conference on
  • Conference_Location
    Chengdu
  • Print_ISBN
    0-7803-9587-5
  • Electronic_ISBN
    0-7803-9587-5
  • Type

    conf

  • DOI
    10.1109/ITST.2006.288778
  • Filename
    4068777