128×128 pixels image sensor for on-sensor-compression

Author

Hamamoto, Takayuki ; Ohtsuka, Yasuhiro ; Aizawa, Kiyoharu

Author_Institution

Dept. of Electr. Eng., Tokyo Univ., Japan

Volume

1

fYear

1998

fDate

4-7 Oct 1998

Firstpage

493

Abstract

We have been investigating a novel integration of sensing and compression on an image sensor. By integration, the number of pixels in the image signal that has to be readout from the sensor can be significantly reduced, and the integration, can consequently increase the pixel rate of the sensor. We present a new compression sensor which has 128×128 pixels. We have made the prototype based on a column parallel architecture and improved the processing circuits of the new prototype to achieve lower power dissipation and higher processing speed in comparison with our previous prototypes. It is verified that the processing circuits can be operated at 5000 frames/second

Keywords

CMOS image sensors; VLSI; data compression; digital signal processing chips; image coding; parallel architectures; 0.7 micron; 128 pixel; 16384 pixel; CMOS process; VLSI; column parallel architecture; compression sensor; image compression; image sensor; image signal; on-sensor-compression; pixel rate; power dissipation; processing circuits; processing speed; Circuits; High-resolution imaging; Image coding; Image sensors; Intelligent sensors; Parallel architectures; Pixel; Power dissipation; Prototypes; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Image Processing, 1998. ICIP 98. Proceedings. 1998 International Conference on

Conference_Location

Chicago, IL

Print_ISBN

0-8186-8821-1

Type

conf

DOI

10.1109/ICIP.1998.723542

Filename

723542