IEEE recommended practice for powering and grounding electronic equipment. (Color Book Series - Emerald Book)

Author

Gabara, Thaddeus

Author_Institution

Bell Lab., Lucent Technol., Murray Hill, NJ, USA

fYear

1999

fDate

1999

Firstpage

84

Lastpage

87

Abstract

The harmonic clock signals in a 5.6 Gb/s NRZ (Non Return to Zero) 2⁷-1 pseudo-random data stream are used to injection lock a CMOS LC tank circuit to 2.8 GHz. The data stream is deserialized into two 2.8 Gb/s data streams by a parallel combination of a positive and negative edge flip-flops (FF) clocked with alternate edges of this recovered clock. This architecture offers power savings since the data and clock rate are reduced immediately by a factor of two. A measured Bit Error Rate (BER) of less than 2E-13 at 5.6 Gb/s is achieved using a conventional 0.25 μm CMOS technology

Keywords

CMOS digital integrated circuits; data communication equipment; digital communication; error statistics; flip-flops; synchronisation; 0.25 micron; 2.8 GHz; 2.8 Gbit/s; 5.6 Gbit/s; BER; CMOS LC tank circuit; NRZ pseudo-random data stream; bit error rate; data stream deserialization; harmonic clock signals; injection locked clock/data recovery cell; negative edge flip-flops; parallel combination; positive edge flip-flops; power savings; submicron CMOS technology; Bit error rate; Books; CMOS technology; Circuits; Clocks; Electronic equipment; Flip-flops; Grounding; Optical signal processing; Power systems;

fLanguage

English

Publisher

ieee

Conference_Titel

Integrated Circuits and Systems Design, 1999. Proceedings. XII Symposium on

Conference_Location

Natal

Print_ISBN

0-7695-0387-X

Type

conf

DOI

10.1109/SBCCI.1999.802973

Filename

802973