DocumentCode
3295198
Title
IEEE recommended practice for powering and grounding electronic equipment. (Color Book Series - Emerald Book)
Author
Caldeira, Laércio ; Pimenta, Tales Cleber ; Cotrim, Evandro D C
Author_Institution
Grupe de Microeletronica, Escola Fed. de Engenharia de Itajuba, Brazil
fYear
1999
fDate
1999
Firstpage
88
Lastpage
91
Abstract
This paper presents the design of a 9-bit parallel multiplier based on the Booth´s algorithm using a 3-bit recoding. Although mentioned as “possible” in the literature, there are no references of its implementation. This multiplier offers a higher multiplication speed over the traditional implementation using only 2 bits, and offers a good speed/area ratio
Keywords
delays; multiplying circuits; pipeline arithmetic; 9 bit; Booth´s algorithm; multiplication speed; parallel pipelined multiplier; speed/area ratio; three-bit recoding; Algorithm design and analysis; Digital arithmetic; Digital integrated circuits; Digital signal processing; Electrical capacitance tomography; Signal processing algorithms;
fLanguage
English
Publisher
ieee
Conference_Titel
Integrated Circuits and Systems Design, 1999. Proceedings. XII Symposium on
Conference_Location
Natal
Print_ISBN
0-7695-0387-X
Type
conf
DOI
10.1109/SBCCI.1999.802974
Filename
802974
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