The circuit designs of an SRAM based look-up table for high performance FPGA architecture

Look-up table (LUT) circuits are the core component of all Field Programmable Gate Arrays (FPGA´s) architectures. Although considerable research has been done regarding the high-level architecture of different LUT´s, very little has been done on the circuit-level description of the LUT. Though traditional LUT designs use NMOS transistors to implement pass-gates that save area and increase speed, large LUT designs require several pass gates in series. Unfortunately, multiple pass transistors in series will degrade the logic high level and thus jeopardize signal integrity. This paper explores different circuit-level implementations of the LUT circuitry with consideration towards the relative design trade-offs.