IEEE recommended practice for powering and grounding electronic equipment. (Color Book Series - Emerald Book)

Author

Brambilla, Marco ; Guidi, Daniele ; Liberali, Valentino

Author_Institution

Micro Syst. Archit., Italy

fYear

1999

fDate

1999

Firstpage

124

Lastpage

127

Abstract

This paper describes a multistage FIR decimation filter implemented with a multiplier-free architecture. The filter is designed to be used in ΣΔ A/D converters in submicron CMOS technology. The proposed architecture aims at increasing the operation speed while limiting the power dissipation, thus reducing the injection of switching noise into the substrate and the digital/analog crosstalk

Keywords

CMOS digital integrated circuits; FIR filters; crosstalk; digital filters; digital subscriber lines; high-speed integrated circuits; integrated circuit noise; sigma-delta modulation; ΣΔ A/D converters; ADSL; digital decimation; digital/analog crosstalk reduction; high speed FIR filters; multiplier-free architecture; multistage FIR decimation filter; operation speed; power dissipation; sigma-delta ADCs; submicron CMOS technology; switching noise reduction; Band pass filters; CMOS technology; Crosstalk; Digital filters; Finite impulse response filter; Identity-based encryption; Multimedia systems; Sampling methods; Signal resolution; Telephony;

fLanguage

English

Publisher

ieee

Conference_Titel

Integrated Circuits and Systems Design, 1999. Proceedings. XII Symposium on

Conference_Location

Natal

Print_ISBN

0-7695-0387-X

Type

conf

DOI

10.1109/SBCCI.1999.803103

Filename

803103