A simulation study of source/drain-tie effects on characteristics of self-aligned π-shaped source/drain ultrathin SOI FETs

Author

Eng, Yi-Chuen ; Lin, Jyi-Tsong ; Chang, Tzu-Feng ; Kuo, Chih-Hao ; Lin, Po-Hsieh ; Sun, Chih-Hung ; Chiu, Hsien-Nan ; Chen, Hsuan-Hsu

Author_Institution

Dept. of Electr. Eng., Nat. Sun Yat-Sen Univ., Kaohsiung, Taiwan

fYear

2009

fDate

6-10 July 2009

Firstpage

169

Lastpage

173

Abstract

This paper aims to investigate the performance and reliability trade-off of the self-aligned (SA) pi-shaped source/drain (S/D) ultrathin silicon-on-insulator (UTSOI) field-effect transistors (FETs). Based on the simulations, the S/D-tie effects are crucial to the future of quasi-SOI devices. The preliminary results of electrical characteristics of the SA-piFETs are carefully demonstrated.

Keywords

field effect transistors; semiconductor device reliability; silicon-on-insulator; reliability trade-off; self-aligned pi-shaped source/drain ultrathin SOI FETs; self-aligned pi-shaped source/drain ultrathin silicon-on-insulator field-effect transistors; source/drain-tie effects; Capacitance-voltage characteristics; Dielectric breakdown; Dielectric measurements; Electric breakdown; Electric variables; FETs; High-K gate dielectrics; Leakage current; Rapid thermal annealing; Temperature;

fLanguage

English

Publisher

ieee

Conference_Titel

Physical and Failure Analysis of Integrated Circuits, 2009. IPFA 2009. 16th IEEE International Symposium on the

Conference_Location

Suzhou, Jiangsu

ISSN

1946-1542

Print_ISBN

978-1-4244-3911-9

Electronic_ISBN

1946-1542

Type

conf

DOI

10.1109/IPFA.2009.5232676

Filename

5232676