IEEE recommended practice for powering and grounding electronic equipment. (Color Book Series - Emerald Book)

Author

Bukovjan, Peter ; Marzouki, Meryem ; Maroufi, Walid

Author_Institution

LIP6 Lab., Paris, France

fYear

1999

fDate

1999

Firstpage

206

Lastpage

209

Abstract

This paper presents our Design for Testability reuse approach implemented in the allocation for testability system IDAT. In the context of High-Level Synthesis for Testability, the allocation for testability process mainly consists in searching for the best cost/quality trade-off between the designer requirements and testability means which can be proposed by the system, considering the available components in the library and the possibility of generating additional testability structures. The cost/quality trade-off is also based on the result of the testability analysis process

Keywords

circuit CAD; design for testability; high level synthesis; integrated circuit design; integrated circuit testing; logic testing; DFT reuse; HLS for testability; IDAT testability system; cost/quality tradeoff; design for testability reuse; high-level synthesis; synthesis for testability; testability analysis process; Automatic testing; Circuit testing; Contracts; Costs; Design for testability; Design optimization; High level synthesis; Laboratories; Performance evaluation; System testing;

fLanguage

English

Publisher

ieee

Conference_Titel

Integrated Circuits and Systems Design, 1999. Proceedings. XII Symposium on

Conference_Location

Natal

Print_ISBN

0-7695-0387-X

Type

conf

DOI

10.1109/SBCCI.1999.803123

Filename

803123