Design and analysis of five port router for network on chip

With the technological advancements a large number of devices can be integrated into a single chip. So the communication between these devices becomes vital. The network on chip (NoC) is a technology used for such communication. A router is the fundamental component of a NoC. This paper focuses on the implementation and the verification of a five port router. The building blocks of the router are buffering registers, demultiplexer, First In First Out registers, and schedulers. The scheduler uses the round robin algorithm. The proposed architecture of five port router is simulated in Xilinx ISE 10.1 software. The source code is written in VHDL.