Design and analysis of five port router for network on chip

Author

Swapna, S. ; Swain, Ayas Kanta ; Mahapatra, Kamala Kanta

Author_Institution

Dept. of Electron. & Commun. Eng, Nat. Inst. of Technol., Rourkela, India

fYear

2012

fDate

5-7 Dec. 2012

Firstpage

51

Lastpage

55

Abstract

With the technological advancements a large number of devices can be integrated into a single chip. So the communication between these devices becomes vital. The network on chip (NoC) is a technology used for such communication. A router is the fundamental component of a NoC. This paper focuses on the implementation and the verification of a five port router. The building blocks of the router are buffering registers, demultiplexer, First In First Out registers, and schedulers. The scheduler uses the round robin algorithm. The proposed architecture of five port router is simulated in Xilinx ISE 10.1 software. The source code is written in VHDL.

Keywords

integrated circuit design; network routing; network-on-chip; scheduling; NoC technology; VHDL; Xilinx ISE 10.1 software; buffering registers; demultiplexer; first-in first-out registers; five port router analysis; network-on-chip; round robin algorithm; schedulers; Clocks; Network topology; Ports (Computers); Random access memory; Registers; Routing; System-on-a-chip; network on chip; round robin algorithm; router;

fLanguage

English

Publisher

ieee

Conference_Titel

Microelectronics and Electronics (PrimeAsia), 2012 Asia Pacific Conference on Postgraduate Research in

Conference_Location

Hyderabad

ISSN

2159-2144

Print_ISBN

978-1-4673-5065-5

Type

conf

DOI

10.1109/PrimeAsia.2012.6458626

Filename

6458626