Improving reliability and diminishing parasitic capacitance effects in a vertical transistor with embedded gate

Author

Lin, Jyi-Tsong ; Kuo, Chih-Hao ; Lee, Tai-Yi ; Eng, Yi-Chuen ; Chang, Tzu-Feng ; Lin, Po-Hsieh ; Chen, Hsuan-Hsu ; Sun, Chih-Hung ; Chiu, Hsien-Nan

Author_Institution

Dept. of EE, Nat. Sun Yat-Sen Univ., Kaohsiung, Taiwan

fYear

2009

fDate

6-10 July 2009

Firstpage

75

Lastpage

78

Abstract

We present a new vertical sidewall MOSFET with embedded gate (EGVMOS) to reduce the parasitic capacitance which is the major disadvantage in a conventional VMOS. According to simulations, our EGVMOS can not only achieve about 86.34% and 54.76% reduction at Cgd at VDs = 0.05 V and 1.0 V respectively, but also improves the device reliability due to suppressed kink effects, in comparison with a conventional VMOS.

Keywords

MOSFET; capacitance; semiconductor device reliability; MOSFET; device reliability; embedded gate EGVMOS; kink effects; parasitic capacitance effect diminishing; simulations; vertical transistor; voltage 0.05 V; voltage 1.0 V; CMOS process; Double-gate FETs; Etching; Lithography; MOSFET circuits; Parasitic capacitance; Silicon on insulator technology; Substrates; Sun; Transconductance;

fLanguage

English

Publisher

ieee

Conference_Titel

Physical and Failure Analysis of Integrated Circuits, 2009. IPFA 2009. 16th IEEE International Symposium on the

Conference_Location

Suzhou, Jiangsu

ISSN

1946-1542

Print_ISBN

978-1-4244-3911-9

Electronic_ISBN

1946-1542

Type

conf

DOI

10.1109/IPFA.2009.5232696

Filename

5232696