Investigation of thermal budget impact on core CMOS SRAM device in an embedded FLASH technology

This paper presents insights into the mechanisms of counter doping and gate depletion due to the lateral diffusion of dopants in embedded flash technology. Core SRAM device behavior is modified by the thermal budget needed to process the specific flash dielectrics. Using a nanoprobe technique, the MOS characteristics of failed and good bits used as a reference in actual SRAM cells were measured directly. In the worst cases, it was confirmed that the on-state current of a PMOS was about three orders of magnitude smaller than that of normal bits, and the threshold voltage was of about 0.9 V higher. A selective etching technique using a KOH solution showed these degradations were caused by local gate depletion. The fabrication process flow shows that the thermal treatment used to form the rapid thermal oxidation layer, causing additional thermal budget, can lead to lateral As-dopant diffusion into a B-doped gate. This diffusion can cause work-function shift, as well as the formation of a depletion capacitor at the polysilicon gate oxide interface, while the MOS is biased. Adjusting the N+ implant boundary for the second poly layer to increase the margin has been found to be quite effective in improving the on-state current degradation and increasing yield.