Source-side engineering to increase holding voltage of LDMOS in a 0.5-m 16-V BCD technology to avoid latch-up failure

Author

Chen, Wen-Yi ; Ker, Ming-Dou ; Jou, Yeh-Ning ; Huang, Yeh-Jen ; Lin, Geeng-Lih

Author_Institution

Inst. of Electron., Nat. Chiao-Tung Univ., Hsinchu, Taiwan

fYear

2009

fDate

6-10 July 2009

Firstpage

41

Lastpage

44

Abstract

To avoid latch-up failure in high voltage integrated circuits, a source-side engineering technique for on-chip ESD protection nLDMOS is proposed in this work. Experimental results have been verified in a 0.5-mum 16-V bipolar CMOS DMOS technology. Measurement results from transmission-line-pulsing system show that the proposed source-side engineering method can effectively increase the holding voltage of the nLDMOS from 10.5 V to 16.2 V. Transient-induced latch-up tests show that the proposed source-side engineering technique significantly improves the latch-up immunity of nLDMOS in on-chip ESD protection circuit.

Keywords

CMOS integrated circuits; bipolar integrated circuits; electrostatic discharge; protection; bipolar CMOS DMOS technology; electrostatic discharge; high voltage integrated circuits; latch-up failure; nLDMOS; on-chip ESD protection circuit; size 0.5 mum; source-side engineering method; transient-induced latch-up test; transmission-line-pulsing system; voltage 10.5 V to 16.2 V; CMOS technology; Circuit testing; Electrostatic discharge; Immunity testing; Integrated circuit measurements; Integrated circuit technology; Power supplies; Protection; Silicon; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Physical and Failure Analysis of Integrated Circuits, 2009. IPFA 2009. 16th IEEE International Symposium on the

Conference_Location

Suzhou, Jiangsu

ISSN

1946-1542

Print_ISBN

978-1-4244-3911-9

Electronic_ISBN

1946-1542

Type

conf

DOI

10.1109/IPFA.2009.5232701

Filename

5232701