DocumentCode :
3295908
Title :
300mm wafer Atomic force probe characterization methodology
Author :
Kane, Terence
Author_Institution :
Microelectron. Div., IBM Syst. Technol. Group, Hopewell Junction, NY, USA
fYear :
2010
fDate :
5-9 July 2010
Firstpage :
1
Lastpage :
3
Abstract :
The laboratory practice of employing atomic force probing (AFP) using AFP current imaging and Nanoprobe Capacitance-Voltage Spectroscopy (NCVS) at contact level (CA) for identification of front end of line (FEOL) defects in MOSFET devices, especially for silicon on insulator applications has been extensively detailed. The introduction of Nanoprobe Capacitance Voltage Spectroscopy (NCVS) on bulk silicon wafers and silicon on insulator (SOI) wafers to characterize discrete MOSFET and SOI embedded dynamic ramdom access memory devices (eDRAM) without the time consuming delayering methods of conventional scanning capacitance microscopy have also been highlighted. Typically, this laboratory AFP characterization is employed on die fragments sampled from whole wafers following back end of the line (BEOL) metallization processing and test. The process vintage of this hardware can be as much as three months after the critical FEOL processing has occurred. This paper is intended to describe for the first time the methodology of applying AFP on whole 300 mm wafers at post CA chemical-mechanical polishing (CMP) process level to provide a real time insight into yield issues that would not be detected until subsequent BEOL metallization processing and testing. This new AFP tool would incorporate enhanced features enabling both DC measurements as well as AC capacitance voltage measurements of discrete deep trench embedded DRAM (eDRAM) devices for 32 nm, 28 nm and 20 nm node technologies.
Keywords :
DRAM chips; MOSFET; atomic force microscopy; chemical mechanical polishing; embedded systems; probes; scanning electron microscopy; semiconductor device metallisation; silicon-on-insulator; AC capacitance voltage measurements; AFP current imaging; BEOL metallization processing; MOSFET devices; SOI embedded dynamic ramdom access memory devices; SOI wafers; back end of the line metallization processing; bulk silicon wafers; contact level; discrete deep trench embedded DRAM devices; eDRAM devices; front end of line defect identification; nanoprobe capacitance-voltage spectroscopy; post CA chemical-mechanical polishing process level; scanning capacitance microscopy; silicon on insulator; size 20 nm; size 28 nm; size 300 mm; size 32 nm; time consuming delayering methods; wafer atomic force probe; Capacitance-voltage characteristics; Laboratories; MOSFET circuits; Metallization; Nanoscale devices; Page description languages; Probes; Random access memory; Silicon on insulator technology; Spectroscopy;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Physical and Failure Analysis of Integrated Circuits (IPFA), 2010 17th IEEE International Symposium on the
Conference_Location :
Singapore
ISSN :
1946-1542
Print_ISBN :
978-1-4244-5596-6
Type :
conf
DOI :
10.1109/IPFA.2010.5531988
Filename :
5531988
Link To Document :
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