DocumentCode :
3296104
Title :
A 3-D simulation study of a novel vertical MOSFET with source-tied (STVMOS)
Author :
Tai, Chih-Hsuan ; Lin, Jyi-Tsong ; Eng, Yi-Chuen ; Lu, Kuan-Yu ; Chen, Cheng-Hsin ; Chang, Yu-Che ; Fan, Yi-Hsuan
Author_Institution :
Dept. of Electr. Eng., Nat. Sun Yat-Sen Univ., Kaohsiung, Taiwan
fYear :
2010
fDate :
5-9 July 2010
Firstpage :
1
Lastpage :
6
Abstract :
In this paper, we propose a source-tied vertical MOSFET (STVMOS) by using 3-D simulation. The characteristics of STVMOS are not only similar to the SOI vertical MOSFET (SOI-VMOS), but also have much better thermal reliability. According to TCAD simulation results, we have achieved 70 mV/decade S.S., 145 mV/V DIBL, and more than 109 ION/IOFF current ratio.
Keywords :
MOSFET; circuit simulation; silicon-on-insulator; 3D simulation study; SOI vertical MOSFET; TCAD simulation; source-tied vertical MOSFET; thermal reliability; Costs; Electric variables; Fabrication; Lattices; Lithography; MOS devices; MOSFET circuits; Manufacturing processes; Silicon on insulator technology; Temperature;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Physical and Failure Analysis of Integrated Circuits (IPFA), 2010 17th IEEE International Symposium on the
Conference_Location :
Singapore
ISSN :
1946-1542
Print_ISBN :
978-1-4244-5596-6
Type :
conf
DOI :
10.1109/IPFA.2010.5531997
Filename :
5531997
Link To Document :
https://search.ricest.ac.ir/dl/search/defaultta.aspx?DTC=49&DC=3296104
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