Title :
A novel self-align double gate MOSFET with source/drain tie
Author :
Lin, Po-Hsieh ; Lin, Jyi-Tsong ; Eng, Yi-Chuen ; Chen, Hsuan-Hsu ; Kuo, Chih-Hao ; Sun, Chih-Hung ; Chiu, Hsien-Nan ; Chang, Tzu-Feng ; Chuang, Nai-Chuan
Author_Institution :
Dept. of Electr. Eng., Nat. Sun Yat-Sen Univ., Kaohsiung, Taiwan
Abstract :
In this paper, a novel device architecture, namely novel self-align double gate MOSFET with source/drain tie, is proposed and compared with the ITRS. According to the simulation results, our proposed transistor not only enhances the on/off current ratio, but also decreases the drain induced barrier lowering and subthreshold swing due to the double gate scheme structure.
Keywords :
MOSFET; self-align double gate MOSFET; source-drain tie; Controllability; Electric variables; Electronics industry; Etching; Fabrication; MOSFET circuits; Process design; Roads; Silicon; Sun;
Conference_Titel :
Physical and Failure Analysis of Integrated Circuits, 2009. IPFA 2009. 16th IEEE International Symposium on the
Conference_Location :
Suzhou, Jiangsu
Print_ISBN :
978-1-4244-3911-9
Electronic_ISBN :
1946-1542
DOI :
10.1109/IPFA.2009.5232719
