Title :
Computing the noise figure of most circuits by applying symbolic analysis
Author :
Sánchez-López, C. ; Tlelo-Cuautle, E. ; Díaz-Sánchez, A.
Author_Institution :
INAOE, Mexico
Abstract :
A novel method focused on the symbolic computation of noise figures (NF) for MOS transistor (MOST) analog circuits, is presented. In order to improve the computation time, a pure-nodal-analysis (PNA) method is applied by modeling all the circuit elements using the or. To demonstrate the suitability of the proposed method, two illustrative examples are given, where the NF computed using the proposed method, is compared with the simulation results using HSPICE.
Keywords :
MOS analogue integrated circuits; active networks; integrated circuit modelling; integrated circuit noise; symbol manipulation; MOS transistor circuit NF; MOST analog circuits; PNA method; circuit noise figure computation; or; pure-nodal-analysis; symbolic analysis; symbolic computation; 1f noise; Circuit analysis computing; Circuit noise; Circuit simulation; Degradation; Noise figure; Noise measurement; Presence network agents; Signal to noise ratio; Voltage;
Conference_Titel :
Circuits and Systems, 2002. MWSCAS-2002. The 2002 45th Midwest Symposium on
Print_ISBN :
0-7803-7523-8
DOI :
10.1109/MWSCAS.2002.1187065
