Evaluation of nanowire field-effect transistors for electrostatic discharge (ESD) applications

Author

Liu, Wen ; Liou, Juin J. ; Li, You ; Chung, J. ; Jeong, Y.H.

Author_Institution

Sch. of EECS, Univ. of Central Florida, Orlando, FL, USA

fYear

2010

fDate

5-9 July 2010

Firstpage

1

Lastpage

5

Abstract

Electrostatic discharge robustness of promising nano-devices, the gate-all-around nanowire field-effect transistor and double-gated poly-Si nanowire thin-film transistor, were characterized and compared with FinFETs for the first time using the transmission line pulsing (TLP) technique. Failure analysis of the devices was done by electrical characterization and microscopy inspection.

Keywords

MOSFET; electrostatic discharge; elemental semiconductors; failure analysis; nanowires; silicon; transmission lines; ESD application; FinFET; Si; TLP technique; double-gated poly-Si nanowire thin-film transistor; electrical characterization; electrostatic discharge; failure analysis; gate-all-around nanowire field-effect transistor; microscopy inspection; nanodevice; transmission line pulsing; Double-gate FETs; Electrostatic discharge; Leakage current; Nanoscale devices; Pulse measurements; Robustness; Scanning electron microscopy; Thin film transistors; Transmission electron microscopy; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Physical and Failure Analysis of Integrated Circuits (IPFA), 2010 17th IEEE International Symposium on the

Conference_Location

Singapore

ISSN

1946-1542

Print_ISBN

978-1-4244-5596-6

Type

conf

DOI

10.1109/IPFA.2010.5532007

Filename

5532007