Performance evaluation of the thin film area in an IC wafer fabrication system using Petri nets

Author

Der Jeng, Mu ; Chuang, Chi Liang ; Hung, Wen Yuan

Author_Institution

Dept. of Electr. Eng., Nat. Taiwan Ocean Univ., Taiwan

Volume

4

fYear

1998

fDate

11-14 Oct 1998

Firstpage

3094

Abstract

We use Petri nets to model and evaluate the performance of the thin film area in a real-word IC wafer fabrication system. The major products of the system are 0.44 μm and 0.38 μm 4MB DRAMs. By using a modular approach, the system model is constructed. Several generic net modules are developed. After the system model is obtained, we use the simulation technique to evaluate its performance. The result shows that the error between an actual and simulated machine utilization is mostly less than 6%. As a result, the performance model is validated. The validated model has been adopted to predict the maximal throughput and bottleneck machines

Keywords

Petri nets; integrated circuit manufacture; production control; simulation; thin film devices; DRAM; IC manufacture; IC wafer fabrication; Petri nets; generic net modules; performance evaluation; simulation; thin film; Etching; Fabrication; Integrated circuit modeling; Petri nets; Predictive models; Production facilities; Semiconductor device modeling; Throughput; Transistors; Transportation;

fLanguage

English

Publisher

ieee

Conference_Titel

Systems, Man, and Cybernetics, 1998. 1998 IEEE International Conference on

Conference_Location

San Diego, CA

ISSN

1062-922X

Print_ISBN

0-7803-4778-1

Type

conf

DOI

10.1109/ICSMC.1998.726477

Filename

726477