• DocumentCode
    3297246
  • Title

    Computing The Entire Active Area /power Consumption Versus Delay Trade-Off Curve For Gate Sizing With A Piecewise Linear Simulator

  • Author

    Berkelaar, Miche R C M ; Buurman, Pim H W ; Jess, Jochen A G

  • fYear
    1994
  • fDate
    6-10 Nov 1994
  • Firstpage
    474
  • Lastpage
    480
  • Keywords
    Circuit simulation; Combinational circuits; Computational modeling; Costs; Delay; Energy consumption; Heuristic algorithms; Linear programming; Logic gates; Piecewise linear techniques;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Computer-Aided Design, 1994., IEEE/ACM International Conference on
  • ISSN
    1063-6757
  • Print_ISBN
    0-8186-3010-8
  • Type

    conf

  • DOI
    10.1109/ICCAD.1994.629853
  • Filename
    629853
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3297246