Title :
A Loss Optimization Method Using WD Product for On-Chip Differential Transmission Line Design
Author :
Ito, Hiroyuki ; Okada, Kenichi ; Masu, Kazuya
Author_Institution :
Inst. of Integrated Res., Tokyo Inst. of Technol., Yokohama
Abstract :
This paper proposes a loss optimization method for a high-speed transmission line on Si LSI. One of the most important issues for a transmission line interconnection is loss reduction of signal lines. Characteristics of differential transmission lines are evaluated by on-wafer measurement. It is shown that attenuation characteristics depend on the product of a line width and a line-to-line distance. The simple attenuation model is proposed
Keywords :
elemental semiconductors; integrated circuit interconnections; large scale integration; silicon; LSI; Si; WD product; high-speed transmission line; line-to-line distance; loss optimization method; on-chip differential transmission line design; on-wafer measurement; signal lines loss reduction; transmission line interconnection is; Coplanar transmission lines; Dielectric substrates; Distributed parameter circuits; Integrated circuit interconnections; Optimization methods; Power transmission lines; Propagation losses; Radio frequency; Transmission lines; Wiring;
Conference_Titel :
Signal Propagation on Interconnects, 2006. IEEE Workshop on
Conference_Location :
Berlin, Germany
Print_ISBN :
1-4244-0455-x
Electronic_ISBN :
1-4244-0455-x
DOI :
10.1109/SPI.2006.289225
