Design analysis of novel substrate-triggered GGNMOS in 65nm CMOS process

A novel substrate-trigger GGNMOS structure with increasing the substrate resistance and pumping substrate trigger current using the VDD bus line controlled PMOS is proposed and verified in 65 nm CMOS process. The trigger voltage can be significantly reduced to ~3 V to safely protect the ultrathin gate oxide. The proposed structure has lower overshoot voltage which is helpful to protect the ultrathin gate. The uniform conducting between multi-fingers has greatly enhanced and the failure current can effectively improved by 23.5%.