Design analysis of novel substrate-triggered GGNMOS in 65nm CMOS process

Author

Song, Bo ; Han, Yan ; Li, Mingliang ; Liou, Juin J. ; Dong, Shurong ; Guo, Wei ; Huang, Dahai ; Ma, Fei ; Miao, Meng

Author_Institution

Dept. of ISEE, Zhejiang Univ., Hangzhou, China

fYear

2010

fDate

5-9 July 2010

Firstpage

1

Lastpage

4

Abstract

A novel substrate-trigger GGNMOS structure with increasing the substrate resistance and pumping substrate trigger current using the VDD bus line controlled PMOS is proposed and verified in 65 nm CMOS process. The trigger voltage can be significantly reduced to ~3 V to safely protect the ultrathin gate oxide. The proposed structure has lower overshoot voltage which is helpful to protect the ultrathin gate. The uniform conducting between multi-fingers has greatly enhanced and the failure current can effectively improved by 23.5%.

Keywords

CMOS integrated circuits; integrated circuit design; substrates; CMOS process; VDD bus line controlled PMOS; pumping substrate trigger current; substrate resistance; substrate-triggered GGNMOS; trigger voltage; ultrathin gate oxide; CMOS process; CMOS technology; Design engineering; Electrostatic discharge; MOS devices; MOSFETs; Protection; Robustness; Silicon; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Physical and Failure Analysis of Integrated Circuits (IPFA), 2010 17th IEEE International Symposium on the

Conference_Location

Singapore

ISSN

1946-1542

Print_ISBN

978-1-4244-5596-6

Type

conf

DOI

10.1109/IPFA.2010.5532074

Filename

5532074