Stability of a-Si thin film transistors under negative gate bias stress

Degradation of a-Si thin film transistors under both DC and AC negative gate bias (V_g) stress has been investigated. Different from most previous work, positive threshold voltage (V_th) shift was observed. In DC stress, larger positive V_th shift occurs under more negative V_g stress due to more severe state creation within a relative short stress time. When the stress V_g becomes more negative, the initial positive shift will be followed by significant negative V_th shift due to the dominance of charge trapping. In AC stress, higher frequency (f) brings less device degradation. State creation mechanism dominates within a relative short stress period for low f stresses, or after a long stress time for high f stresses. Otherwise, charge trapping mechanism dominates. High stress temperature enhances both mechanisms. Besides, degradation of the leakage current has also been investigated, which was rarely reported before. It decreases under low f stress but increases under high f stress.