Simple but efficient reconfiguration algorithm for degradable VLSI/WSI arrays

This paper presents an efficient algorithm for the reconfiguration of a two-dimensional degradable VLSI/WSI array with faulty processing elements (PEs). Unlike previous work, the proposed algorithm does not limit the number the physical rows related to the logical row to be constructed, in order to utilize as many fault-free PEs as possible to compensate faulty ones. Also, the row-exclusion process of the state-of-the-art is removed and thus the selection of the row for including into the target array is successfully avoided. The proposed flexible rerouting approach makes the state-of-the-art simplified and improved. Experimental results show that the proposed algorithm is able to generate a larger logical array with the harvest increasing up to 10%. Meanwhile, it runs faster up to 10 times than the existing algorithms cited in this paper.