Estimating the First Voltage Drop for ICs with leakage

Chip technology sets increasingly challenging limits which must not be exceeded by high- and mid frequency power noise of the chip supply voltage. An accurate estimate of the voltage drop following a Delta-I step is therefore very important for modern package development. In this paper we examine simple circuit models where the equations for the voltage fluctuations due to power noise can be solved analytically. Special attention is given to the correct treatment of chip leakage. Also, a comparison is made between circuit models that simulate the chip Delta-I noise by a constant current source and models that simulate delta-I noise by using a switching resistor