Title :
Low Complexity Equivalent Circuit Models for VLSI Interconnects
Author :
Telescu, M. ; Tanguy, N. ; Brehonnet, P. ; Vilbe, P. ; Calvez, L.C.
Author_Institution :
LEST UMR CNRS, Brest
Abstract :
In this paper we present a technique for generating low complexity equivalent circuit models for VLSI circuit interconnects via the Laguerre-Gram model order reduction (MOR) method developed by our team. We discuss model passivity and equivalent circuit implementation and then show the advantages of our method in preserving important signal parameters such as rise time, delay and overshoot
Keywords :
VLSI; computational complexity; equivalent circuits; integrated circuit interconnections; matrix algebra; Laguerre-Gram model order reduction; VLSI interconnects; low complexity equivalent circuit models; model passivity; Admittance; Circuit simulation; Delay effects; Electronic mail; Equivalent circuits; Integrated circuit interconnections; Reduced order systems; Robust stability; Transfer functions; Very large scale integration;
Conference_Titel :
Signal Propagation on Interconnects, 2006. IEEE Workshop on
Conference_Location :
Berlin
Print_ISBN :
1-4244-0455-x
Electronic_ISBN :
1-4244-0455-x
DOI :
10.1109/SPI.2006.289242
