Throughput analysis of pipelined multiprocessor modules

A feasible form of parallel architecture would be one which consists of several pipeline stages, each of which is a multiprocessor module of a large number of processing elements (PEs). In many applications, such as real-time image processing and dynamic control, the optimized computing structure would be in this form. In the present study, the performance of a parallel processing model of such an organization has been analyzed. In particular, the effect of interstage communication on throughput of the model has been investigated to suggest an efficient way of transferring data between stages. The numerical results obtained in this study could be a useful guideline for designing a parallel computer system consisting of pipeline stages each of which contains a large number of PEs